library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;



entity sram_read_mux IS
    GENERIC(
       num_requester      : natural := 4
    );
    PORT( 
       in_sram_rq_addr    : in std_logic_vector((18*num_requester)-1 DOWNTO 0);
       
       schedule_nr        : in   std_logic_vector (num_requester-1 DOWNTO 0);
       
       out_sram_rq_addr     : out   std_logic_vector(17 DOWNTO 0)
    );
end sram_read_mux;



architecture Behavioral of sram_read_mux is
 
    
begin
        
  with std_logic_vector'(schedule_nr) select out_sram_rq_addr <=
    in_sram_rq_addr(17 downto 0) when (num_requester-1 downto 1 => '0') & '1',
    in_sram_rq_addr(35 downto 18) when (num_requester-1 downto 2 => '0') & "10",
    in_sram_rq_addr(53 downto 36) when (num_requester-1 downto 3 => '0') & "100",
    (17 downto 0 => '0') when others;



end Behavioral;